1. Field of the Invention
The present invention relates generally to design verification tools, and in particular to design verification systems and methods for developing systems on chips.
2. Description of the Related Art
The complexity of systems on chips (SoCs) continues to grow as increasing numbers of transistors are incorporated into SoCs. SoC implementations can include one or more processors and a variety of peripherals, all integrated onto one semiconductor substrate. The peripherals can be in various states of operation at the same time that the processor(s) are performing numerous other operations. The number of possible states in the SoC, all of which must generally provide correct operation, increases exponentially with complexity. Such complexity must be tested during the design and manufacture of the SoC to provide reasonable assurance that the SoC will function as designed and that the design is correct.
One common methodology used for the testing and debugging of SoCs is based on the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard test access port and boundary-scan architecture, also known as joint test action group (JTAG). Debug controllers often utilize signals that are compliant with the JTAG protocol for testing actual physical SoCs. Prior to fabricating an actual SoC, most SoCs are modeled and simulated in a variety of simulation platforms. For example, various emulators have been developed that offer the ability to simulate SoC designs prior to fabricating the SoC in silicon. However, some of these emulators do not include a JTAG interface. Furthermore, debug controllers which execute commands and scripts for testing an actual physical SoC, typically use a JTAG interface to interface to the SoC when the SoC is fabricated. However, these debug controllers are not able to use this JTAG interface to communicate with emulators that lack a JTAG interface.
As the size of SoCs continues to increase, the amount of testing and debugging that needs to be performed also increases. Some tests may be lengthy and involve many lines of code. In addition, software developers are often required to use a low-level JTAG protocol compliant language to write debug and testing commands that will be incorporated into various testing scripts. Furthermore, the scripts that are used to test a hardware model of a SoC typically cannot be reused when a development board with a fabricated SoC is being tested. This means that the software developer will be required to write new scripts to test the physical SoC, instead of being able to reuse the existing scripts that were used to test the model of the SoC.